1. Field of the Invention
This invention relates to the field of microprocessor design, and micro-architechure and more specifically to a method and apparatus for manipulating a Status Word register of an instruction set processor which has a pipelined execution unit.
2. PRIOR ART
One of the most popular math co-processor chips, the Intel 80387, implements the 80x87 instruction set. The x87 instruction set is a complex instruction set which provides a programmer with hardware support for a wide variety of numeric functions ranging from floating point adds and multiplies to transcendental functions. The x87 Instruction Set Architecture defines a status register which is updated after the execution of each numeric instruction, and which reflects the status of the machine at the completion of the instruction. The Status Word is "programmer visible" which means that after the execution of an instruction, a programmer can access each bit of the Status Word to determine the overall state of the floating point unit at any given point.
Detailed information with respect to x87 microprocessors and the x87 instruction set in general can be found in publications such as Microprocessors published by Intel Corporation and the 80386 Microprocessor Handbook published by McGrawHill.
As shown in FIG. 1, the Status Word is 16 bits wide and is broken up into several distinct components. Each component relays specific information about the status of the floating point unit after an execution of an instruction. The 16 bits of the Status Word contained in the Status Word register are updated after the completion of each instruction. In reference to FIG. 1, bits B.sub.0 -B.sub.5 of the Status Word are known as the exception flags. These bits are flags for indicating when the floating point unit has detected an exception while executing an instruction. The six exceptions can be masked by masking bits corresponding to each exception found in the floating point unit control word.
B.sub.6 of the Status Word is the stack flag (SF). This bit is used to distinguish invalid operations due to stack overflow or underflow. When B.sub.6 (SF) is set, B.sub.9 or (C1) distinguishes between stack overflow or underflow.
B.sub.7 of the Status Word is known as the error summary bit (ES). The (ES) bit is set if an unmasked exception occurs, i.e., when any of bits B.sub.0 -B.sub.5 of the Status Word are set, and the flagged exception is unmasked.
B.sub.15 of the Status Word is known as the busy bit (B). The busy bit B is provided for compatibility with the 8087 instruction set and carries the same value as the (ES) bit, B.sub.7 of the Status Word.
B.sub.14 and B.sub.8, B.sub.9 and B.sub.10 of the Status Word are the four numeric condition codes, C0-C3. Where B.sub.14 corresponds to C3 and Bits 10, 9 and 8 correspond to C2-C0, respectively. Instructions which perform arithmetic operations update C0-C3 differently to reflect the outcome of each executed instruction. Each instruction updates C0-C3 in its own distinct manner. Instruction updating of C0-C3 is well defined and detailed in the handbook Microprocessors published by Intel Corporation.
Bits B.sub.13, B.sub.12 and B.sub.11 are the top of stack bits (TOS). They provide three bits of data indicating which of eight floating point data registers supplied by x87 instruction set microprocessors is the current top of the stack.